A Low Power Gate Level Full Adder Module
نویسنده
چکیده
A standard cell based gate level synchronous full adder design is presented in this paper. The main highlight of the article is that the proposed full adder realization is found to be better in terms of power-delay product (PDP), even in comparison with the full adder element that has been made available as part of two commercial standard cell libraries viz. the high-speed 130nm Faraday (UMC) bulk CMOS process technology and the low Vt but inherently power optimized 65nm STMicroelectronics bulk CMOS process. The fundamental ripple carry adder (RCA) topology is considered to demonstrate the power efficiency of our full adder module vis-à-vis many other recently proposed full adder module designs. Keywords—Full adder, Semi-custom design, Low power design, Power-delay product.
منابع مشابه
Low power high speed hybrid CMOS Full Adder By using sub-micron technology
In the recent year, many other new circuits are proposed using less number of transistors with less delay and extremely low power requirement. An adder consisting with less transistors don't give full swing outputs for all input combinations and there is difference in output level for various combinations and these circuits have very low driving capabilities. other circuits also are proposed in...
متن کاملUltra-Low Cost Full Adder Cell Using the nonlinear effect in Four-Input Quantum Dot Cellular Automata Majority Gate
In this article, a new approach for the efficient design of quantum-dot cellular automata (QCA) circuits is introduced. The main advantages of the proposed idea are the reduced number of QCA cells as well as increased speed, reduced power dissipation and improved cell area. In many cases, one needs to double the effect of a particular inter median signal. State-of-the-art designs utilize a kind...
متن کاملEvaluation of Power Delay Product for Low Power Full Adder Circuits based on GDI Logic Cell using Mentor Graphics
This paper presents high speed and low power full adder cells designed with an alternative internal logic structure and Gate Diffusion Input (GDI) logic styles and hybrid CMOS logic style that lead to have a reduced Power Delay Product (PDP). The main design objective for this adder module is not only providing low-power dissipation and high speed but also full-voltage swing. In the first desig...
متن کاملEvolutionary QCA Fault-Tolerant Reversible Full Adder
Today, the use of CMOS technology for the manufacture of electronic ICs has faced many limitations. Many alternatives to CMOS technology are offered and made every day. Quantum-dot cellular automata (QCA) is one of the most widely used. QCA gates and circuits have many advantages including small size, low power consumption and high speed. On the other hand, using special digital gates called re...
متن کاملComparison of Single Bit 14T and 8T Full Adder for Low-Power VLSI Design
This paper presents a new design for 14 transistor single bit full adder, implemented using five transistor XNOR/XOR cell and transmission gate multiplexer. For transmission gate multiplexer complementary gate control signals are required and in 14 transistor full Adder both XOR and XNOR signals are generated. XNOR/XOR cell shows high power consumption than single XNOR gate. So, 8 transistor fu...
متن کامل